In many types of logic and computer circuit applications, it is desired to have circuit means for delaying an information signal containing a data stream of binary digits. One device for accomplishing this purpose is a shift register device circuit. Such shift register devices are made up of successive stages. In the semiconductor circuit realization of such a register, each of the stages typically includes both semiconductor transmission gate elements and semiconductor inverter elements.
During operation of a shift register device, each stage at any moment of time contains a binary digital bit of information represented by a relatively "high" vs. "low" voltage level at a node in the stage. Each such bit of information is retained in its corresponding stage for a single periodic cycle of a clock pulse voltage source which drives all the various stages simultaneously, and each stage feeds its information bit periodically (at the termination of each clock cycle) to the next succeeding stage. Thus, in response to a sequence of these clock pulses, each bit of information sequentially passes through the entire shift register from an initial input register stage to a final output register stage. During each clock cycle, moreover, the input stage receives a fresh bit of information from a binary digital source of information, while the output stage shifts and delivers its bit of information to a utilization device.
Shift register devices are generally classified as "static" or "dynamic", respectively, depending upon whether or not the information contained in the various stages is retained in the event that the driving clock voltages suddenly become locked in one phase of a cycle, that is, the driving clocks stop. Thus, in a static shift register, all the information present at any moment in the register is stored and remains there in case the driving clock pulse voltages suffer phase stoppages; and this information will then resume being shifted, and thereafter continue to be shifted, through the register device in the event the clock pulse voltages resume their cycling; that is, the shift register device then takes up where the device had left off when the driving clocks had stopped. In a dynamic shift register, however, the information in the various stages at any moment is irretrievably lost in case the clock pulse voltages temporarily stop. Thus, static shift registers have the advantage over dynamic shift registers insofar as retention of information during driving clock stoppage is concerned. On the other hand, static shift registers in the art of semiconductor circuits require more semiconductor circuit elements per stage and hence require more space one the semiconductor wafer (chip) in which the shift register circuit is built. For example, each stage of a static shift register circuit which is driven by a two-phase clock ordinarily requires four electrical transmission gate elements plus four electrical inverter elements; whereas a two-phase dynamic register requires only two such gates plus two such inverters. This added semiconductor wafer space requirement of static shift register circuits presents a serious problem because manufacturing yields in the semiconductor art decrease sharply with increased semiconductor wafer area.
It would therefore be desirable to have a semiconductor shift register circuit which requires fewer circuit components per stage than the static shift register circuits of the prior art, but which retains the information in case of driving clock stoppage.